The present invention relates to a control storage (CS) for storing a microprogram (MP) in a system for processing data under control of the microprogram.
As IC manufacturing technology has advanced, the integration factor for providing logic on a chip has been remarkably increased. The integration factor of an IC memory has particularly been increased. However, the reliability of the IC memory has not been increased at the same rate, but reliability per IC rather tends to be decreased. A high density IC is an important factor in compacting a product and the demand for high density is continuously growing. Accordingly, it is clearly important in the manufacture of a memory IC to utilize high density IC techniques while preventing a reduction in the reliability of the product.
As a method for preventing a reduction of the reliability, or even enhancing that reliability, it has been known to use a single bit error check and correction and a multiple-bit error check technique using a Hamming code. This error checking and correcting (ECC) technique has been used in main memories to prevent the reduction of or enhance the reliability of the high density IC memories provided as the main memories.
In a control storage (CS) for storing a microprogram (MP), the ECC technique has been rarely used because the IC memory used in the control storage CS is much more expensive than the IC memory used as the main memory because of the high speed requirement and the demand for reducing the capacity of the control storage CS is strong. Accordingly, it has been common to add parity bits which need a smaller number of bits than the check bits for the ECC technique.
However, in recent years, the microprogram not only executes the instruction words, but also executes particular routines in the program, which is done in firmware, and the number of steps of the microprogram has increased by the enhancement of maintenance and diagnosing functions. Accordingly, the required capacity of the control storage CS has been necessarily increasing. Consequently, higher speed and higher density IC memories are being used as the control storage CS. As a result, the reliability of the control storage CS has decreased and error detection by the use of a parity check routine cannot assure normal system operation because of increasing errors. Accordingly, the need for an error recovery method has become a continuing problem to be resolved.
Besides the ECC method, the known error recovery methods include a retry method for an intermittent error and a refresh method involving rewriting which makes use of a property inherent in the control storage CS that the content thereof is not variable. However, none of these methods is completely effective to detect a solid error and hence the complete recovery by the ECC method has been demanded.